Athlon 64

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The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003<ref name="release">Template:Cite web</ref>. It is the third processor to bear the name "Athlon", and the immediate successor to the Athlon XP<ref name="AthlonXP">Template:Cite web</ref>. The second processor (after the Opteron) to implement AMD64 architecture and the first 64-bit processor targeted at the average consumer<ref name="nameRelease">Template:Cite web</ref>, it is AMD's primary consumer microprocessor, and competes primarily with Intel's Pentium 4, especially the "Prescott" and "Cedar Mill" core revisions. It is AMD's first K8, eighth-generation processor core for desktop and mobile computers<ref name="K8CPUID">Template:Cite web</ref>. Despite being natively 64-bit, the AMD64 architecture is backward-compatible with 32-bit x86 instructions<ref name="Architecture">Template:Cite web</ref>. Athlon 64s have been produced for Socket 754, Socket 939, Socket 940 and Socket AM2.

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History

All of the 64-bit processors sold by AMD so far have their genesis in the "K8" project. It was internally referred to as both "K8" and "Sledgehammer," though Sledgehammer was also used to refer to a particular tapeout.

The Athlon 64 was originally codenamed "ClawHammer" by AMD<ref name="nameRelease" />, and was referred to as such internally and in press releases. The first Athlon 64 FX was based on the first Opteron core, "SledgeHammer". Both cores, produced on a 130 nanometer process, were first introduced on September 23, 2003. The models first available were the FX-51, fitting Socket 940, and the 3200+, fitting Socket 754<ref name=CNETlaunch">Template:Cite web</ref>. Like the Opteron it was based on, the Athlon FX-51 required buffered RAM, increasing the final cost of an upgrade<ref name="Buffered">Template:Cite web</ref>. The week of the Athlon 64's launch, Intel released the Pentium 4 Extreme Edition, a CPU designed to compete with the Athlon 64 FX<ref name="P4EE">Template:Cite web</ref>. The Extreme Edition was widely considered a marketing ploy to gain publicity away from AMD, and was quickly nicknamed among some circles the "Emergency Edition"<ref name="EmergencyEdition">Template:Cite web</ref>. Despite a very strong demand for the chip, AMD was plagued by early manufacturing difficulties that made it difficult to deliver Athlon 64s in quantity. In the early months of the Athlon 64 lifespan, AMD could only produce one hundred thousand chips per month<ref name="Production">Template:Cite web</ref>. However, it was very competitive in terms of performance to the Pentium 4, with magazine PC World calling it the "fastest yet"<ref name="FastestYet">Template:Cite web</ref>. "Newcastle" was released soon after ClawHammer, with half the Level 2 cache<ref name="Newcastle">Template:Cite web</ref>.

On June 1, 2004, AMD released new versions of both the ClawHammer and Newcastle core revisions for the newly-introduced Socket 939, an altered Socket 940 without the need for buffered memory<ref name="Sockets939and940">Template:Cite web</ref>. Socket 939 offered two main improvements over Socket 754: the memory controller was altered with dual-channel architecture<ref name="DualChannel">Template:Cite web</ref>, doubling peak memory bandwidth, and the HyperTransport bus was increased in speed from 800 MHz to 1000 MHz<ref name="Socket939">Template:Cite web</ref>. Socket 939 also was introduced in the FX series in the form of the FX-55<ref name="FX-55">Template:Cite web</ref>. At the same time, AMD also began to ship the "Winchester" core, based on a 90 nanometer process.

Core revisions "Venice" and "San Diego" succeeded all previous revisions on April 15, 2005. Venice, the lower-end part, was produced for both Sockets 754 and 939, and included 512 KiB of L2 cache<ref name="Venice">Template:Cite web</ref>. San Diego, the higher-end chip, was produced only for Socket 939 and doubled Venice's L2 cache to one MiB<ref name="SanDiego">Template:Cite web</ref>. Both were produced on the 90 nm fab process<ref name="Que8thGen">Template:Cite web</ref>. Both also included support for the SSE3 instruction set<ref name="SSE3">Template:Cite web</ref>, a new feature that had been included in the rival Pentium 4 since the release of the Prescott core in February 2004<ref name="PrescottSSE3">Template:Cite web</ref>. In addition, AMD overhauled the memory controller for this revision, resulting in performance improvements as well as support for newer DDR RAM<ref name="VeniceMemController">Template:Cite web</ref>.

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Dual core Athlon 64s

Main article: Athlon 64 X2

On April 21, 2005, less than a week after the release of Venice and San Diego, AMD announced its next addition to the Athlon 64 line, the Athlon 64 X2<ref name="X2Announce">Template:Cite web</ref>. Released on May 31, 2005<ref name="X2PressRelease">Template:Cite web</ref>, it too initially had two different core revisions available to the public, Manchester and Toledo, the only appreciable difference between them being the amount of L2 cache<ref name="X2Cores">Template:Cite web</ref>. Both were released only for Socket 939<ref name="X2939">Template:Cite web</ref>. A response to Intel's dual core Pentium D, the Athlon 64 X2 was received very well by reviewers and the general public, with a general consensus emerging that AMD's implementation of multi-core was superior to that of the Pentium D<ref name="X2Review1">Template:Cite web</ref><ref name="X2Review2">Template:Cite web</ref>. Some felt initially that the X2 would cause market confusion with regard to price points since the new processor was targeted at the same "enthusiast," US$350 and above market<ref name="Pricing">Template:Cite web</ref> already occupied by AMD's existing socket 939 Athlon 64s <ref name="MarketConfusion">Template:Cite web</ref>. AMD's official breakdown of the chips placed the Athlon X2 aimed at a segment they called the "prosumer", along with digital media fans<ref name="X2PressRelease" />. The Athlon 64 was targeted at the mainstream consumer, and the Athlon FX at gamers. The Sempron budget processor was targeted at value-conscious consumers<ref name="Positioning">Template:Cite web</ref>.

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DDR2

The Athlon 64 had been maligned by some critics for some time because of its lack of support for DDR2 SDRAM, an emerging technology that had been adopted much earlier by Intel<ref name="DDR2criticism">Template:Cite web</ref>. AMD's official position was that the CAS latency on DDR2 had not progressed to a point where it would be advantageous for the consumer to adopt it<ref name="DDR2rejected">Template:Cite web</ref>. AMD finally remedied this gap with the "Orleans" core revision, the first Athlon 64 to fit Socket AM2, released on on May 23, 2006<ref name="AM2launch">Template:Cite web</ref>. "Windsor", an Athlon 64 X2 revision for Socket AM2, was released concurrently. Both Orleans and Windsor have 1 MiB of L2 cache per core<ref name="AM2cache">Template:Cite web</ref>. The Athlon 64 FX-62 was also released concurrently on the Socket AM2 platform<ref name="FX62">Template:Cite web</ref>. Socket AM2 also consumes less power than previous platforms, and also supports AMD's virtualization technology<ref name="AM2Benefits">Template:Cite web</ref>.


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Features

There are four variants: Athlon 64, Athlon 64 FX, Mobile Athlon 64 (later renamed "Turion 64") and the dual-core Athlon 64 X2<ref name="Family">Template:Cite web</ref>. Common among the Athlon 64 line are a variety of instruction sets including MMX, SSE, SSE2, 3DNow!, and AMD64<ref name="DataSheet">Template:Cite web</ref>. All Athlon 64s with the exception of the original ClawHammer release also support the NX bit, a security feature named "Enhanced Virus Protection" by AMD<ref name="NXBit">Template:Cite news</ref>. And as implementations of the AMD64 architecture, all Athlon 64 variants are able to run 16 bit, 32 bit x86, and AMD64 code, through two different modes the processor can run in: "Legacy mode" and "long mode". Legacy mode runs 16-bit and 32-bit programs natively, and long mode runs 64-bit programs natively, but also allows for 32-bit programs running inside a 64-bit operating system<ref name="Modes">Template:Cite web</ref>. All Athlon 64 processors feature 128 kibibytes of level 1 cache, and at least 512 kibibytes of level 2 cache<ref name="DataSheet" />.

The Athlon 64 features an on-die memory controller<ref name="Architecture" />, a feature not previously seen on x86 CPUs. Not only does this mean the controller runs at the same clock rate as the CPU itself, it also means the electrical signals have a shorter physical distance to travel compared to the old northbridge interfaces<ref name="VsNorthbridge">Template:Cite web</ref>. The result is a significant reduction in latency (response time) for access requests to main memory<ref name="LatencyReduction">Template:Cite web</ref>. The lower latency is often cited as one of the advantages of the Athlon 64's architecture over those of its competitors<ref name="MemoryLatency">Template:Cite web</ref>.

Translation Lookaside Buffers (TLBs) have also been enlarged (40 4k/2M/4M entries in L1 cache, 512 4k entries)<ref name="HammerPreview">Template:Cite web</ref>, with reduced latencies and improved branch prediction, with four times the number of bimodal counters in the global history counter<ref name="Modes" />. This and other architectural enhancements, especially as regards SSE implementation, improve instruction per cycle (IPC) performance over the previous Athlon XP generation<ref name="Modes" />. To make this easier for consumers to understand, AMD has chosen to market the Athlon 64 using a PR rating (Performance Rating) system, where the numbers roughly map to Pentium 4 performance equivalents, rather than actual clock speed<ref name="PRrating">Template:Cite web</ref>.

Image:Athlon-64-Lenara-CG.jpg
Athlon 64 CG ("Newcastle") in Socket 754

Athlon 64 also features CPU speed throttling technology branded Cool'n'Quiet, a feature similar to Intel's SpeedStep that can throttle the processor's clock speed back to facilitate lower power consumption and heat production<ref name="CnQ">Template:Cite web</ref>. When the user is running undemanding applications and the load on the processor is light, the processor's clock speed and voltage are reduced. This in turn reduces its peak power consumption (max TDP set at 89 W by AMD) to as low as 32 W (stepping C0, clock speed reduced to 800 MHz) or 22W (stepping CG, clock speed reduced to 1 GHz). The Athlon 64 also has an Integrated Heat Spreader (IHS) which prevents the CPU core from accidentally being damaged when mounting and unmounting cooling solutions. With prior AMD CPUs a CPU shim could be used by people worried about damaging the core.

The No Execute bit (NX bit) supported by Windows XP Service Pack 2<ref name="WinNX">Template:Cite web</ref>, Windows XP Professional x64 Edition, Windows Server 2003 x64 Edition, and Linux 2.6.8 and higher is also included, for improved protection from malicious buffer overflow security threats. Hardware-set permission levels make it much more difficult for malicious code to take control of the system. It is intended to make 64-bit computing a more secure environment.

The Athlon 64 CPUs have been produced with 130 nm and 90 nm SOI process technologies. All of the latest chips (Winchester, Venice and San Diego models) are on 90 nm. The Venice and San Diego models also incorporate dual stress liner technology (an amalgam of strained silicon and 'squeezed silicon', the latter of which is not actually a technology) co-developed with IBM.

As the memory controller is integrated onto the CPU die, there is no FSB for the system memory to base its speed upon. Instead, system memory speed is obtained by using the following formula (using the ceiling function):

<math>\frac{\mathrm{CPU~speed}}{\left\lceil\frac{\mathrm{CPU~multiplier}}{\mathrm{DRAM~divider}}\right\rceil}=\mathrm{DRAM~speed}</math>

In simpler terms, the memory is always running at a set fraction of the CPU speed, with the divisor being a whole number. An 'FSB' figure is still used to determine the CPU speed, but the RAM speed is no longer directly related to this 'FSB' figure (known otherwise as the LDT).

To summarize, the Athlon 64 architecture features two buses from the CPU. One is the HT bus to the northbridge connecting the CPU to the chipset and device attachment bus (PCIe, AGP, PCI) and the other is the memory bus which connects the on-board memory controller to the bank of either DDR or DDR2 DRAM. Review the following reference for more detail: AMD Athlon 64 architecture

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Athlon 64 FX

The Athlon 64 FX is positioned as a hardware enthusiast product, marketed by AMD especially toward gamers<ref name="FXbrief">Template:Cite web</ref>. Unlike the standard Athlon 64, all of the Athlon 64 FX processors have their multipliers completely unlocked<ref name="FXMultiplier">Template:Cite web</ref>. The FX line is now dual-core, starting with the FX-60<ref name="FXDualCore">Template:Cite web</ref>. The FX always has the highest clock speed of all Athlons at its release<ref name="FXClock">Template:Cite web</ref>.

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Athlon 64 X2

Main article: Athlon 64 X2
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Mobile Athlon 64

Main article: Turion 64
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Sockets

  • 754: The Athlon 64 value/budget line, 64-bit memory interface (Single-Channel)
  • 939: Athlon 64 performance line, Athlon 64 X2s, and newer Athlon 64 FXs, 128-bit memory interface (Dual-channel)
  • 940: Opteron and old Athlon 64 FX, 128-bit memory interface - requires registered DDR memory
  • Socket F: Opteron, 1207 Pins
  • Socket AM2: Athlon 64/Athlon 64 FX/Athlon 64 X2/Sempron, 940 Pins (Not compatible with Socket 940); the first AMD socket to use DDR2 SDRAM.
  • Socket 4x4: To be released in late 2006 - early 2007. Will consist of two AM2 sockets; designed for Athlon 64 X2 dual-core processors, essentially giving the user four available processor cores.

At the introduction of Athlon 64 in September 2003, only Socket 754 and Socket 940 (Opteron) were ready and available. The onboard memory controller was not capable of running unbuffered (non-registered) memory in dual-channel mode at the time of release; as a stopgap measure, they introduced the Athlon 64 on Socket 754, and brought out a non-multiprocessor version of the Opteron called the Athlon 64 FX, as a multiplier unlocked enthusiast part for Socket 940, comparable to Intel's Pentium 4 Extreme Edition for the high end market.

In June 2004, AMD released Socket 939 as the mainstream Athlon 64 with dual-channel memory interface, leaving Socket 940 solely for the server market (Opterons), and relegating Socket 754 as a value/budget line, for Semprons and slower versions of the Athlon 64. Eventually Socket 754 replaced Socket A for Semprons.

In May 2006, AMD released Socket AM2, which provided support for the DDR2 memory interface. Also, this marked the release of AMD's Virtualization technology.

In August 2006, AMD released Socket F for Opteron server CPU which uses the LGA chip form factor.

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Athlon 64 FX models

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Sledgehammer (130 nm SOI)

  • CPU-Stepping: C0, CG
  • L1-Cache: 64 + 64 KiB (Data + Instructions)
  • L2-Cache: 1024 KiB, fullspeed
  • MMX, Extended 3DNow!, SSE, SSE2, AMD64
  • Socket 940, 800 MHz HyperTransport (HT800)
  • Registered DDR-SDRAM required
  • VCore: 1.50/1.55 V
  • Power Consumption (TDP): 89 Watt max
  • First Release: September 23, 2003
  • Clockrate: 2200 MHz (FX-51, C0), 2400 MHz (FX-53, C0 and CG)
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Clawhammer (130 nm SOI)

  • CPU-Stepping: CG
  • L1-Cache: 64 + 64 KiB (Data + Instructions)
  • L2-Cache: 1024 KiB, fullspeed
  • MMX, Extended 3DNow!, SSE, SSE2, AMD64
  • Socket 939, 1000 MHz HyperTransport (HT1000)
  • VCore: 1.50 V
  • Power Consumption (TDP): 89 Watt (FX-55:104 Watt)
  • First Release: June 1, 2004
  • Clockrate: 2400 MHz (FX-53), 2600 MHz (FX-55)
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San Diego (90 nm SOI)

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Toledo (90 nm SOI)

Dual-core CPU

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Windsor (90 nm SOI)

Dual-core CPU

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Athlon 64 models

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ClawHammer (130 nm SOI)

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Newcastle (130 nm SOI)

Also possible: ClawHammer-512 (Clawhammer with partially disabled L2-Cache)

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Winchester (90 nm SOI)

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Venice (90 nm SOI)

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San Diego (90 nm SOI)

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Orleans (90 nm SOI)

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External links

Retrieved from "http://mediacoder.sourceforge.net/wiki/index.php/Athlon_64"

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